In a programmable logic device there is need for an optional inverter, that is, a circuit which can either pass a signal in its non-inverted form or can invert the signal, as selected by a user. FIG. 1 shows such a circuit. P-channel transistor T1 and N-channel transistor T2 form a standard CMOS inverter. Memory cell M1 provides complementary signals which control pass-gate transistors T3 and T4 such that circuit 101 provides either the non-inverted input signal through transistor T3 or the inverted input signal through transistor T4. In a 5-volt system, when input line IN carries about 5 volts, transistor T2 is on and transistor T1 is off. Thus the inverted output line INV is connected to ground or 0 volts. When input line IN carries about 0 volts, transistor T1 is on and T2 is off, so that line INV is connected to VCC or 5 volts. In either case there is no path from VCC to ground through transistors T1 and T2 because one of them is off. However, transistor characteristics are usually chosen so that when the input signal on line IN is switching through the range of 2 to 3 volts, both transistors T1 and T2 are partly on and there is a current path from power to ground. Even when the non-inverted path through transistor T3 has been chosen, the CMOS inverter formed by transistors T1 and T2 causes a current drain when the input signal is switching.
Other optional inverters are known. FIG. 2 shows another prior art optional inverter in which transistors T1 and T2 of a standard CMOS inverter generate the complement of the input signal on line IN. When the signal on line IN is about 5 volts, transistor T7 is on and the inverted signal from memory cell M1 is provided as the output signal on line OUT. When the signal on line IN is about 0 volts, transistor T8 is on, and provides the non-inverted signal from memory cell M1 to line OUT. If memory cell M1 carries a logical 0 value, the circuit of FIG. 2 is a non-inverting buffer, while if memory cell M1 carries a logical 1 value (5 volts), the circuit is an inverter. In both embodiments (FIGS. 1 and 2), the CMOS inverter comprising transistors T1 and T2 drains power when the signal on line IN switches through the range of 2 to 3 volts, regardless of whether the output is to be inverted from the input signal. In integrated circuit devices it is desirable to decrease power use where possible.